A Novel Technique to Reduce Power Consumption of Flash ADC

Flash architecture generally achieves the highest conversion speed and represents an ideal design approach for realizing high-speed data converters. However, power consumption always confines its utilization in low-power applications. The primary objective of this book is to showcase a new high-performance comparator for the low-power application of Flash ADC. Moreover, by employing the proposed comparator, the designed Flash ADCs eliminate a power-hungry reference-ladder network. The secondary objective is to offer a novel power reduction technique for high-speed Flash ADC, which examines the inactive comparators in the Flash ADC and disables them to save unnecessary power consumption.